Retiming arrangement for SDH data transmission system

ABSTRACT

A retiming arrangement for use in a demultiplexer in an SDH data transmission system uses Bit Justification data, and not Pointer data, to modify a recovered clock signal and generate a clock signal for retiming purposes. The invention is especially for use in enabling third party users to carry primary rate timing data across an SDH network.

BACKGROUND OF THE INVENTION

The present invention relates to a retiming arrangement for use in anSDH (Synchronous Digital Hierarchy) data transmission system. Inparticular the invention is concerned with the provision of anarrangement by which third parties wishing to use an SDH link which iscontrolled by another operator may carry their own timing and otherinformation across that network.

Third party timing is defined when the timing to be carried in a primaryrate signal originates from a source which is not synchronous with thesource used to time the SDH network. Third party timing is thereforeplesiochronous to the bearer clock.

In SDH, primary rate signals are mapped into high bit rate SynchronousTransport Modules (STM-N), at the insertion point of the network usingvirtual containers (VC) and tributary units (TU), the size and type ofwhich depends on the data rate of the signal being carried. Many ofthese TU's are multiplexed together into a single STM-N. At theextraction point the STM-N is demultiplexed and demapped back intoprimary rate signals. However the signals suffer from phase andfrequency distortions which effect the quality of the signal when usedfor transporting timing information. The key component in SDH systemsused to reduce these distortions is the so-called desynchronizer orretiming arrangement.

SUMMARY OF THE INVENTION

The present invention arose in an attempt to improve the systemdisclosed in our co-pending British patent application 9114841.1,published as GB 2257603A on Jan. 13, 1993, the contents of which arehereby incorporated into this application by this reference. The aim ofthe present invention is to permit third parties using their own primaryrate timing source to carry timing information over an SDH network whichis operated by a first party. This is not currently possible and asshown in FIG. 1B of the above mentioned document a separate channelneeds to be provided to carry this timing information.

In the above mentioned document either both pointer data and BitJustification data are used for retiming purposes, or neither such data,timing being provided at the primary rate output on the assumption thatthe primary rate signal is synchronised to the bearer. The applicantshave appreciated that if Bit Justification data is used without thePointer data, then an SDH network can be adapted to carry such thirdparty timing information without providing a separate link.

In one aspect the invention provides a retiming arrangement for an SDH(Synchronized Digital Hierarchy) data transmission system by which thirdparties may use an SDH link, comprises an input (5) for receipt of amultiplexed STM (Synchronous Transport Module) a signal, a clockrecovery circuit (20) for recovering a clock signal from the STM signal,a demultiplexer (21) for demultiplexing the STM signal into a pluralityof TU (Tributary Unit) signals, a pointer processor (25) for readingpointer data from a TU signal, a bit dejustifier (28) for reading bitjustification data from the TU signal, a buffer store (30) with a storemonitor (34) in which store (30) the processor TU data is storedtemporarily before being clocked out at a retimed clock rate, whereinsaid retiming arrangement is characterised in that means (32) forgenerating the retimed clock signal (31), are provided, which means (32)includes three phase adjust inputs (φ1, φ2, φ3) which are connected tothe pointer processor (25), bit dejustifier (28) and store monitor (34)respectively whereby only the read bit justification data generated bythe bit dejustifier (28) is used (on phase adjust input φ2) to modifythe recovered clock signal (23) and generate the retimed clock signal(31).

An embodiment of the invention will now be described by way of examplewith reference to the drawings in which;

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 shows schematically an SDH network together with a third partyuser; and

FIG. 2 is a block diagram illustrating a retiming arrangement accordingto the invention.

DETAILING DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1 an SDH network comprises a network timing source 1which feeds an, e.g., 2 MHz signal into an exchange 2. The exchangefeeds 2 Mbit signals over N, two as shown, signal connections 3 into anSDH multiplexer 4. The multiplexed STM-N signal is then fed over an SDHbearer 5 to an SDH demultiplexer 6. The exchange 2 is also connected tothe SDH multiplexer 4 by a control line 7 which synchronizes the bearer5 at the 2 MHz clock rate. Within the demultiplexer 6 the signal isconverted back into the 2 Mbit/s primary rate format and fed over lines8 to an exchange 9. A line 10 corresponding to line 7 is provided forderiving timing information from the bearer.

In addition and by using a retiming arrangement as will be described, athird party user can use the SDH network for conveying timing and otherdata from a private network 11. A private timing source 10, which is notsynchronous with the network timing source 1, transmits timing signals,i.e. primary rate signals at 1.544Mbit/s or 2.048 Mbit/s through a link12 to the SDH multiplexer 4. After demultiplexing the timing signals areconveyed along line 13 to the private network 14. It can be seen that bycomparing FIG. 1 to FIG. 1b of our copending British applicationmentioned previously that the timing information from the third partyhad in the past to be carried along a separate link.

Referring now to FIG. 2, the demultiplexer 6 together with thedesynchronizer or retiming arrangement is shown in more detail. Amultiplexed STM-N signal is input firstly to a clock recovery circuit 20where a so called ‘TO’ clock signal is stripped off on to line 23. Afterthat the multiplexed signal is then passed to a demultiplexer 21 whereit is demultiplexed into N low order signals, so called TU-11 or TU12data dependent on the bit rate of the primary signals (1.544 Mbit/s or2.048 Mbit/s respectively). Each of the N primary rate signals 22 isthen passed to a retiming arrangement. Although as shown only one sucharrangement is provided for the one demultiplexer, in practice aseparate circuit would be provided for each of the N channels 22. The TUdata is firstly passed to a pointer processor 25. The pointer processoris part of the high order path adaptation (HPA) and functions tointerpret differences in phase and frequency between the clocks at thepoint of insertion and point of extraction of the SDH network, which areencoded by the TU pointer. “Pointers” are described in more detail inour co-pending British application referred to previously. In essenceeach virtual container or VC signal is allowed to float within theaggregate stream of bytes, such that the starting point of the VC withinthe overall SDH signal can change from one signals' successive frame toanother. The pointer value determines the start point of the particularVC. The pointer processor 25 in addition receives an enable signal online 26 which functions as a dynamic flag to indicate whether the datain any particular TU signal is true or real data, as opposed to being anoverhead.

After the pointer processor, the resulting VC data is transferred to abit dejustifier 28 which forms part of the low order path overhead(LPA).

Bit justification is defined within CCITT standards. In essence bitjustification data provides a means of indicating where a 2 Mbit datasignal is located within a VC. For example at the point of injectioninto the system there may be more traffic data than can be accommodatedwithin the byte space allocated for that purpose. Any overflow may beaccommodated within the justification overhead bytes. Bit justificationis used to provide a means of indicating that traffic data is locatedwithin the justification overhead bytes and that this needs to beretrieved before the signal can be sent on for further processing.Following bit dejustification the remaining data is passed to an elasticstore 30 where temporary phase transients due to gaps caused by theextraction of overhead and justification bytes are absorbed. The primaryrate signal 29, retimed by means to be described is then read out of theelastic store on lines 8 or 13, using the numbering shown in FIG. 1.

A phase locked loop 32 is operative to take as an input the bearerreference TO clock signal recovered at stage 20 and to output a modifiedread clock signal for use in retiming data out of the elastic store 30.The read clock signal 31 can be derived in any one of a number of ways.The phase lock loop 32 includes three phase adjust inputs φ1, φ2 and φ3.These are connected to the pointer processor 25, bit dejustifier 28 anda store monitor 34 respectively. Which, or what combination of input areused is controlled by a mode selector 36 which operates respectiveswitches for each of the phase adjust inputs.

Operation of the circuit will firstly be described with reference tonormal—i.e. non third party use. In a first mode the φ3 input isselected and the store monitor 34 is arranged to ensure that the elasticstore 30 remains half filled such that the rate of the data leaving thestore equals the rate at which it is entering the store. In this way theprimary rate timing signal can be accurately reproduced.

In a second mode phase inputs φ1 and φ2 are selected, with φ3 beingdisabled. In this mode the recovered bearer clock on line 23 is useddirectly with phase adjustments being made by the pointer processor 25and bit dejustifier 28.

When the above circuit is to be used for primary rate retiming for athird party user, neither of the above modes can be used. The abovementioned desynchronizer operation produces TU pointer adjustmentresulting in a phase transient of about 3.5 micro seconds per pointer atthe output of the SDH network. A good desynchroniser design will attemptto limit the rate of leak out of this phase by limiting thecorresponding frequency shift of the desynchroniser PLL. This limitingnormally takes the phase form of narrowing the PLL bandwidth resultingin closely spaced pointer adjustments of opposite polarity cancellingout and having no net effect on the final output. However, pointeradjustments of opposite polarity that are not widely separated (by afactor greater than the RC time constant of the PLL) will not cancel.

Within synchronized SDH networks TU-1 pointer changes will occur as aresult of slowly varying phenomenon such as temperature effects onoptical fibres and multiplexer equipment.

While much equipment is tolerant of these phase steps introduced toprimary rate signals there are some systems which being designed forplesiochronous digital hierarchy (PDH) transmission which only employbit justification techniques, have a tolerance of less than onemicrosecond. The invention offers a means by which the effects of TU-1pointer changes can be eliminated leaving the output phase response ofthe desynchronizer to be comparable with that of bit dejustification.

In the third mode of operation, for use in primary rate retiming forthird parties, the mode selector 36 is operated such that, in normalthird party operation, only the φ2 input is enabled such that only bitdejustification data is used to adjust the TO clock frequency. While asshown the φ1 input is disabled, in an alternative arrangement the PLLmay be operative to respond to φ1 adjustments, but to cancel eachoccurrence with one of equal size and of opposite polarity. Thusoperation is in similar manner as a PDH demultiplexer. As a safeguard,input φ3 is also enabled, but the store monitor 34 and elastic store 30are operated in a different way as will now be described.

As long as the SDH network remains synchronization, ignoring thepointers will have no long term effect on the timing carried within theprimary rate signal. In fact any temporary loss of synchronization orlarge amounts of wander in the SDH network will be accommodated withinthe elastic store 30. This is designed to be relatively large, typicallyin excess of 40 microseconds to accommodate the maximum permitted wanderin an SDH path. If SDH network synchronization is lost for a long periodof time the effect would eventually be an underflow or overflow of theelastic store 30. The store monitor 34 would then initiate a leak out ofphase to recover capacity in the elastic store 32. Thus the storemonitor 34 operates in a different way to that described with referenceto normal, or non third-party use. As an alternative the capacity couldbe recovered by reverting the desynchronize operation temporarily backto one of the fist two modes—i.e. using only the store monitor on the φ3input or adjustment using both φ1 and φ2 for a limited period of time.

What is claimed is:
 1. A retiming arrangement for a synchronous digitalhierarchy (SDH) data transmission system by which third parties use anSDH link, comprising: an input for receipt of a multiplexed synchronoustransport module (STM) signal; a clock recovery circuit for recovering aclock signal from the STM signal; a demultiplexer for demultiplexing theSTM signal into a plurality of tributary unit (TU) signals; a pointerprocessor for reading pointer data from a TU signal; a bit dejustifierfor reading bit justification data from the TU signal; a buffer storewith a store monitor in which store the processor TU data is storedtemporarily before being clocked out at a retimed clock rate; aphase-locked loop having three phase adjust inputs; and a mode selectorand switching circuit for connecting the pointer processor, bitdejustifier, and store monitor, in different modes, to the three phaseadjust inputs, said circuit, in a first mode, being operative forconnecting the bit dejustifier to one of the phase adjust inputs forselecting only the read bit justification data generated by the bitdejustifier to modify the recovered clock signal and generate theretimed clock signal.
 2. The retiming arrangement according to claim 1,wherein the store is an elastic store, and wherein the phase-locked loopis further operative for checking for an underflow and overflowcondition of the store and for making an adjustment to the retimed clocksignal so as to maintain capacity within the store.
 3. The retimingarrangement according to claim 1, wherein the circuit is operative, in asecond mode, for connecting the bit dejustifier and the pointerprocessor to two of the phase adjust inputs to modify the recoveredclock signal using both the read bit justification data and the pointerdata to generate the retimed clock signal.
 4. The retiming arrangementaccording to claim 1, wherein the phase-locked loop is operative, in athird mode of operation, for checking that the store is approximatelyhalf full and for adjusting the rate of the retimed clock signal so asto maintain the half full condition.
 5. The retiming arrangementaccording to claim 1, wherein the phase-locked loop receives therecovered clock signal at one of the phase adjust inputs and generatesthe retimed clock signal at an output, and adjusts the frequency of theoutput at another of the phase adjust inputs.
 6. The retimingarrangement according to claim 1, wherein the phase-locked loop isfurther operative for nullifying the effect of utilizing pointer data bymodifying the recovered signal twice using pointer data of equalamplitude but opposite polarity.